The present invention relates to the sizing of transistors in integrated circuits to optimize the efficiency thereof over a broader range of operating parameters. The preferred embodiment of this invention relates to an integrated circuit memory device, specifically a dynamic access memory ("DRAM"), and particularly the output circuit thereof.
Integrated circuit memory devices, (sometimes called "chips") store data and provide it to an output of the chip. The memory can be a static or dynamic RAM, or other types of memory such as read-only memory ("ROM"). Generally speaking, the prior art output circuits for such memories usually include two large field effect transistors ("FETs") at the output, and data that has been obtained from the memory cells within the chip are applied to these output transistors to drive a fairly substantial current at the output node. The capacitance associated with the output node is typically on the order of 50 picofarads. In the past, the time to drive a data output node was a manageable percentage of the total access time of a DRAM. With increasing memory capacity, however, and decreasing access times, it is important to keep the necessary time to drive the output node relatively small. Thus, it is important to drive the output pin or output node with a relatively large current provided by the output stage of the chip.
The design of any integrated circuit must necessarily take into consideration the operating parameters and restrictions imposed on the entire chip. A chip or integrated circuit will be connected to receive a source of operating voltage which in the field of MOS transistors is generally called V.sub.CC. The operating voltage V.sub.CC may be 5.0 volts (nominally), but there is no certainty that this power supply voltage will stay constant. It must be assumed that there will be variations in V.sub.CC, and integrated circuits in the DRAM field at least must meet specifications for the power supply voltage going higher than nominal. It may safely be assumed that the design must accommodate a power supply voltage of as low as 4.5 volts or as much as 5.5 volts (or more). These are referred to as "low" and "high" voltages, with the "nominal" voltage between them.
Whenever the power supply voltage rises to high voltage the transistors inherently work faster and draw more current. The same result occurs when temperature declines--and a wide temperature range is another operational requirement that must be considered in the design of the chip. The normal operating temperature can be referred to as "nominal," between low and high extremes. In order to accommodate the high currents which result at the extremes of the operating ranges specified for the chip, transistors are constructed to draw known currents at those extreme parameters. The result has been that the circuitry provides somewhat less than optimum performance at operating conditions that are less extreme (or nominal). With regard to the output circuit, in the past where the output circuitry is sized to draw maximum current at six volts, for example, the circuit would draw less current at four volts. By sizing the transistors in this prior art fashion, the current delivered when the power supply voltage is four volts is less than the current delivered when the power supply voltage is six volts. Accordingly, it has taken a longer time to drive the data output node with the power supply at four volts than at six volts.
It will be seen therefore that this aspect of integrated circuit design militates against achieving maximum performance at the nominal power supply output voltage. This factor unduly limits the speed of DRAMs since significant time is spent driving the data output node in the output circuit by using prior art techniques.
Accordingly, the main object of the present invention is to provide data output circuitry which can operate at high efficiency in nominal operating voltage specifications and temperature specifications even though it is designed to accommodate higher power supply voltages and lower temperatures. As used herein, "nominal" voltage is not limited to 5.0 volts, but for the expected, normal, typical voltage of the power supply.
It may generally be stated that an object of the present invention is to provide an improved output control circuit for an integrated circuit memory.
A more specific object of the present invention is to provide an output circuit so that the output transistors can be sized for maximum speed at a less extreme power supply voltage than the circuit is required to accommodate. Illustratively, if the power supply voltage is nominally five volts but may rise to six volts, an object of the present invention is to provide maximum speed at five volts instead of maximum speed at six volts.